Designing customized microprocessors for fixed-point computation

Abstract

This paper proposes a method to optimize application-specific microprocessors for fixed-point computations. Fixed-point word-length optimization is a well-known research area that aims to find the optimal trade-offs between accuracy and hardware cost in bitwidth allocation signals in fixed point circuits. This work proposes a methodology to combine word-length optimization with application-specific processor customization. The goal is to optimize the following parameters in the processor architecture: (1) datatype word-lengths, (2) size of register-files and (3) architecture of the functional units. Multi-level evolutionary algorithms are employed to perform the optimization. To facilitate evaluation, a new processor design environment was developed that supports necessary customization flexibility to realize and evaluate the proposed methodology. The experimental results show that for five evaluated benchmarks, the proposed methodology can reduce the number of consumed LUTs and flip-flops by an average of 11.9% and 5.1%, respectively, while reducing the latency by an average of 33.4%.