A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

Abstract

In this paper, we present a novel single event upset (SEU) hardened latch. The latch consists of a new 12 transistor (12T) SEU hardened storage cell and a C-element. It is insensitive to single event transient (SET) affecting it's internal and output nodes. The differential writing capability of the proposed storage cell is very attractive for designing flip-flops. In addition, we present a high performance SEU hardened D type edge triggered flip-flop, particularly attractive for low data switching activity. The flip-flop utilizes an output feedback connection to the input register stage, in order to reduce power consumption at low data switching activity and eliminate the hold time constraint from traditional clocked CMOS register. We have implemented the proposed latch and the flip-flop in a standard 65 nm CMOS technology. We have investigated power consumptions, propagation delay, SET sensitivity and the area penalty of the proposed latch and flip-flop comparing with the recently reported SEU hardened latches and flip-flops. The proposed latch exhibits as much as 17% lower power-delay product (PDP) compared to recently reported SEU hardened latch, and the proposed flip-flop exhibits lower or comparable PDP compared to recently reported SEU hardened flip-flop while offering more robustness to particle induced SET.