Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI:10.1109/ASPDAC.2011.5722275

Jian-wei Fang, S. Sapatnekar

引用次数: 8

Abstract

Gate oxide breakdown is a major cause of reliability failures in future nanometer-scale CMOS designs. This paper develops an analysis technique that can predict the probability of a functional failure in a large digital circuit due to this phenomenon. Novel features of the method include its ability to account for the inherent resilience in a circuit to a breakdown event, while simultaneously considering the impact of process variations. Based on standard process variation models, at a specified time instant, this procedure determines the circuit failure probability as a lognormal distribution. Experimental results demonstrate this approach is accurate compared with Monte Carlo simulation, and gives 4.7–5.9× better lifetime prediction over existing methods that are based on pessimistic area-scaling models.

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在栅极氧化物可靠性分析中考虑电路固有弹性和工艺变化

栅极氧化物击穿是未来纳米级CMOS设计可靠性失效的主要原因。本文开发了一种分析技术，可以预测由于这种现象而导致的大型数字电路功能故障的概率。该方法的新特点包括它能够考虑电路对击穿事件的固有弹性，同时考虑工艺变化的影响。该程序基于标准过程变化模型，在指定的时间瞬间，确定电路失效概率为对数正态分布。实验结果表明，与蒙特卡罗模拟相比，该方法是准确的，并且比基于悲观面积缩放模型的现有方法的寿命预测提高4.7 - 5.9倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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