Performance optimization of RingFET using LDD implantation

Abstract

Semiconductor industry has explored various novel device structures to extend CMOS scaling. Circular geometry devices have been recently proposed to improve immunity to short channel effects without compromising planarity. In this work, one such circular geometry device called RingFET is considered and its performance enhancement through Lightly Doped Drain (LDD) implantation is sought using 3D TCAD simulations. RingFET has a circular gate geometry, which has better short channel immunity compared to conventional MOSFET structure mainly because of the elimination of side interface regions, that gives rise to trap induced leakages. This reduces the OFF current consequently, making RingFET better in the short channel regime. RingFET structure has a planar geometry but differs only lithographically with respect to MOSFET. This makes RingFET an interesting device to explore. The impact of LDD and its variants are studied with respect to DC and AC analysis using 3D TCAD simulations. The parameters under consideration are ON current, OFF current, Ion/Ioff ratio, sub-threshold swing (SS), transconductance (gm) and unity gain frequency (fT).