A fast comparator with integrated small dual hysteresis and offset control

V. Barzinska
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引用次数: 1

Abstract

This paper presents the design of a fast comparator, where the dual hysteresis and the digital offset control are integrated in a source degenerated preamplifier stage. The selected architecture of the preamplifier stage, followed by a differential symmetrical OTA allowed easily to be achieved design requirements as 8mV hysteresis, 1σ input random offset of 0.58mV, range of ±35mV additional digital offset control with 5mV step, 30ns propagation delay, while the power dissipation is 90μW and the block area is 0.015mm2 at 0.18μm CMOS technology. The source degenerating resistors in the preamplifier stage can be used to create dual or single, digitally programmed hysteretic comparators.
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集成了小双迟滞和偏移控制的快速比较器
本文提出了一种快速比较器的设计,该比较器将双滞后和数字偏置控制集成在一个源退化前置放大器级中。在0.18μm CMOS工艺下,采用前置放大器级和差分对称OTA的结构可轻松实现8mV迟滞、0.58mV的1σ输入随机偏置、±35mV的附加数字偏置控制、5mV步进、30ns传播延迟、功耗为90μW、块面积为0.015mm2的设计要求。前置放大器级的源退化电阻可用于创建双或单,数字编程的滞回比较器。
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