Optimal Sizing of CMOS LC Voltage Controlled Oscillator by means of Genetic Algorithm

Abstract

This paper presents an optimal design approach for a 0.35µm CMOS cross-coupled differential voltage-controlled oscillator (CMOS LC-VCO) with the aim of achieving low phase noise, high figure-of-merit (FOM), and low power consumption. To address the design challenges, a metaheuristic Genetic Algorithm (GA) is used to determine the optimal dimensions of the LC-VCO's components, specifically the channel length and width of the MOS transistors, which enable the circuit to perform at its best. The proposed LC-VCO is verified through ADS simulation software and achieves - 124dBc/Hz at 1MHz offset frequency from a carrier frequency of 2.6 GHz with a power consumption of 8 mW. A comparison with other published works is also provided to highlight the performance of the proposed design.