Design of an efficient power distribution network for the UltraSPARC-I microprocessor

Abstract

The design, implementation, and verification of the power distribution network for the 5.2 million transistor UltraSPARC-I microprocessor is described. A novel simulation method allows rapid identification of exact layout locations with potential electromigration or excessive voltage drop problems. Hierarchical verification capabilities of this approach are utilized to design an efficient and robust distribution of V/sub dd/ and V/sub ss/ across a large die, in the face of stringent IR drop and floorplanning constraints. A comprehensive methodology for power distribution and management, along with seamless integration of the power distribution into existing CAD tools throughout the design cycle results in correct-by-construction power networks for cell libraries and functional blocks, area efficient power interconnections and reduced time-to-market due to correction of all reliability failures in the power networks prior to mask generation.