Investigation of process induced stress in the channel of a SiGe embedded source/drain Ge-FinFET architecture

Abstract

In this work, a Ge Fin channel Field Effect Transistor (FinFET) with Silicon-Germanium (SiGe) embedded source/drain region has been studied using Sentaurus Technology Computer Aided Design (TCAD) process and device simulator from Synopsys and the impact of SiGe stressor material induced channel stress on the device performance has been investigated thoroughly. It is found that the SiGe embedded source/drain regions induce tensile stress in the channel that helps to improve the n-channel device performance. The amount of induced channel stress has been found to depend on the relative dimensions of the gate, source/drain, and Fin channel regions. A significant improvement of channel stress and hence the device performance, in terms of drive current (Ion) and Ion/Ioff ratio, is observed for higher source/drain volume and thinner Fin width device structure due to the enhancement of electron mobility by the induced stress, indicating better performance of the transistor. Also, more than 3× drive current improvement compared to unstrained device has been achieved for 25% Ge content in the SiGe stressor material.