VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM)

Abstract

Throughout the design life cycle of an integrated circuit (IC), verification plays a crucial part in affirming the functionalities of the features implemented based on the architecture used. In the case of a processor with advanced microarchitectural features implemented, a simulation-based approach is taken for its functional verification. Functional verification increases the level of confidence in conformance of the processor design to its specification. This paper presents the approach that could be utilized in the VLSI design course in Universiti Tunku Abdul Rahman (UTAR). More specifically, Universal Verification Methodology (UVM) is utilized for the verification methodology of the RISC-V processor implementation in this work.