Reconfigurable router using RLBS algorithm

Abstract

Multiprocessor System-On-Chips (MPSoCs) is an emerging technology. They provide support to the design complexity of embedded systems. MPSoCs will combine several types of processor cores and data memory units of widely different sizes, leading to a very heterogeneous architecture. As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC) system. In traditional solutions interconnections are realized using a bus structure. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementations. Bus starts to be narrow and in the worst case it begins to block traffic. In NoC technology the bus structure is replaced with a network which is similar to the Internet. Nowadays NoCs are a well established research topic and several implementations have been proposed. Some techniques are proposed to improve NoC performance in terms of latency and throughput while others are proposed to improve area utilization and power consumption. An important research in NoC design is the trade off between area/power and performance. In order to improve performance some techniques tend to increase the number of buffers, this method increases area and power consumption. This paper introduces new router architecture called the Reconfigurable router, which improves the performance of the overall network using the same amount of available buffers but in more efficient way. Therefore there is no need to increase the size of which cause high power consumption, area overheads, and complex logic.