Performance analysis of low power and high speed 16-Bit CRC Generator using GDI technique

Abstract

In this paper, we present the implementation of high speed 16-Bit CRC Generator architecture using gate diffusion input technique. The main objective of CRC generator is used for error detection in communication systems. The Gate Diffusion Input logic is a technique that are used to reduce transistor count and power consumption of sequential circuits. The hardware component of CRC is consists of group of D flip-flops. Here the gate diffusion input logic based D flip-flop is a basic cell to design a CRC Generator, maintaining low complexity of logic design. The design of 16 Bit CRC generator using GDI technique reports 59.95 % improvement in power consumption and 19% reduction in transistor count compared to conventional CMOS technique.