Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories

Abstract

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising non-volatile memory technologies and shows potential as an SRAM replacement. However, targeted for advanced CMOS technologies such as the 14nm FinFET node, time-zero variability is a major concern for these memory technologies. In this paper, we investigate the STT-MRAM variability with respect to different technology scenarios. We show the impact of these variations on the bit error rate of the emerging STT-MRAM memories.