{"title":"A prototyping system for high performance communication systems","authors":"Matthias Dörfel, R. Hofmann","doi":"10.1109/IWRSP.1998.676673","DOIUrl":null,"url":null,"abstract":"Presents a prototyping platform for high-performance communication systems together with a design methodology. Based on a formal design entry and nonfunctional design goals such as execution time and overall system cost, a software/hardware partitioning is generated and its performance is estimated with formal models. Valid partitionings are then implemented on a prototyping platform which is based on a heterogeneous multiprocessor system and a reconfigurable FPGA board. Using model-based optimization and monitoring, each partitioning is evaluated and the results are fed back in the generation and estimation of new partitionings.","PeriodicalId":310447,"journal":{"name":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1998.676673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
Presents a prototyping platform for high-performance communication systems together with a design methodology. Based on a formal design entry and nonfunctional design goals such as execution time and overall system cost, a software/hardware partitioning is generated and its performance is estimated with formal models. Valid partitionings are then implemented on a prototyping platform which is based on a heterogeneous multiprocessor system and a reconfigurable FPGA board. Using model-based optimization and monitoring, each partitioning is evaluated and the results are fed back in the generation and estimation of new partitionings.
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