Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits

Abstract

In Today’s scenario the use of adiabatic approach in electronic circuit is to minimize the power consumption in order to obtain low power VLSI circuits. There are different types of adiabatic logic circuit used for low power consumption. The comparative power consumption of adiabatic logic using Two Phase Adiabatic Static Clocked logic (2PASCL) and Positive Feedback Adiabatic Logic (PFAL) is proposed here. In digital design flip flops are the main components responsible for storing in all SOCs. The power consumption of D-Flip flop and T-Flip flop is compared using both the adiabatic topologies. From the results obtained using tanner EDA, full adder T-Flip flop is designed in both the topologies. The result shows that T-Flip flop using 2PASCL is more power efficient than T-Flip flop using PFAL.