Design of a Digital Decimation Filter with High Speed and Low Complexity

2021 IEEE 3rd International Conference on Circuits and Systems (ICCS) Pub Date : 2021-10-29 DOI:10.1109/ICCS52645.2021.9697215

Xiaochen Li, Ying Shang, Ruilian Zhao, Beili Jiang

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引用次数: 2

Abstract

Digital filter is an important component of analog-to-digital converter. The speed and complexity of digital decimation filter have a great influence on Sigma Delta analog-to-digital converter. In view of this situation, a design of high speed and low complexity digital filter is presented in this paper. A three stages cascaded architecture is adopted to reduce the number of half-band filters by increasing the downsampling rate of cascaded integrator-comb filter. The cascaded integrator-comb filter adopts a serial-parallel mixed structure to improve the speed of data processing. In order to reduce the complexity of digital filter, a novel sine compensation filter is proposed to compensate the passband attenuation and the multipliers of half-band filter are designed by time division multiplexing technique. The simulation results and analysis show that this design meets the performance requirements and its speed is increased by four times. Compared with the same type of filters, the number of multipliers, adders and registers has decreased by 45%, 31% and 26% respectively.

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一种高速低复杂度数字抽取滤波器的设计

数字滤波器是模数转换器的重要组成部分。数字抽取滤波器的速度和复杂度对Sigma Delta模数转换器有很大的影响。针对这种情况，本文提出了一种高速、低复杂度的数字滤波器设计方案。采用三级级联结构，通过提高级联积分器梳状滤波器的下采样率来减少半带滤波器的数量。级联积分器梳状滤波器采用串并联混合结构，提高了数据处理速度。为了降低数字滤波器的复杂度，提出了一种新的正弦补偿滤波器来补偿通带衰减，并采用时分复用技术设计了半带滤波器的乘法器。仿真结果和分析表明，该设计满足性能要求，速度提高了4倍。与同类型滤波器相比，乘法器、加法器和寄存器的数量分别减少了45%、31%和26%。

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2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)

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