Software Compilation Using FPGA Hardware: Register Allocation

Abstract

Malicious attackers are constantly attacking software compilers and attempting to exploit various security vulnerabili-ties. By executing carefully chosen machine instructions already present in the program, an attacker can perform harmful actions arbitrarily. In this paper, we propose hardware/software codesign techniques to perform software compilation steps in hardware, specifically the register allocation step on a Field Programmable Gate Array (FPGA). Our experiment incorporates two key features: 1) Advanced RISC Machine (ARM) instruction set architecture (ISA)-based register allocation algorithms to calculate variable liveness as well as map virtual registers to physical registers and 2) the feasibility of executing the register allocation algorithms on a Cyclone V FPGA. Our experimental results show the timing efficiency and resource efficiency - while diminishing security risks - when performing register allocation of the gcd program on the FPGA.