A 675 /spl mu/W 5 GHz low-voltage BiCMOS synchronized ring oscillator based prescaler

Abstract

This paper presents the design and the experimental measurements of a 5 GHz divide-by-4 prescaler for 802.11a and HiperLAN2 applications. The presented circuit is implemented in a 0.25μm BiCMOS SiGe process from STMicroelectronics. The prescaler is optimized for low power operation. It uses a Synchronized Ring Oscillator architecture based on two low-voltage differential bipolar latches with PMOS loads. The prescaler draws 520 μA from a 1.3 V power supply, its operating frequency is from 4.7 GHz to 6.8 GHz with a sensitivity of -10 dBm, and its efficiency is about 10 GHz/mW.