VLSI implementation of digital receivers for paging and PCS

Abstract

Just as advanced digital communications techniques have been employed to increase the capacity of cellular systems, similar concepts are being used to extend the capacity and introduce multispeed and multiformat capabilities for portable messaging systems in the paging, and narrowband PCS arena. In this paper, we review the problem of designing digital receivers for these markets, where product life cycles are dramatically shortening. We first take a brief look at the standards uses in paging and narrowband PCS. Then, we examine the structure of digital receivers, focusing on the structure of baseband digital modems. We then propose and demonstrate a design methodology for the VLSI implementation of key algorithm modules using dataflow modeling and behavioral synthesis. Finally, we conclude with some observations on design technologies for PCS chipsets.