{"title":"An on-line CORDIC based 2-D IDCT implementation using distributed arithmetic","authors":"Yi Yang, Chunyan Wang, M. Ahmad, M. Swamy","doi":"10.1109/ISSPA.2001.949836","DOIUrl":null,"url":null,"abstract":"This paper presents a cost-effective VLSI architecture for a two-dimensional (2-D) inverse discrete cosine transform (IDCT) core based on a modified on-line CORDIC algorithm. In order to have a low hardware complexity and to provide a good performance, the proposed design is based on the row-column decomposition approach and distributed arithmetic (DA). By reformulating the 1-D IDCT functions using the CORDIC approach, the proposed design requires about 60% less ROM than the conventional DA-based IDCT without using CORDIC. In our architecture the on-line algorithm is used to further reduce the area and to enhance the computation speed. The core operates on blocks of 8/spl times/8 pixels, with 12-bit and 8-bit precision for inputs and outputs, respectively. The proposed design has been synthesized by using 0.35-/spl mu/m CMOS technology. The simulation results show that the core for IDCT can run at 150 MHz with 60 Mpixel/s throughput, while meeting the requirement of the H.26x standard.","PeriodicalId":236050,"journal":{"name":"Proceedings of the Sixth International Symposium on Signal Processing and its Applications (Cat.No.01EX467)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Sixth International Symposium on Signal Processing and its Applications (Cat.No.01EX467)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSPA.2001.949836","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper presents a cost-effective VLSI architecture for a two-dimensional (2-D) inverse discrete cosine transform (IDCT) core based on a modified on-line CORDIC algorithm. In order to have a low hardware complexity and to provide a good performance, the proposed design is based on the row-column decomposition approach and distributed arithmetic (DA). By reformulating the 1-D IDCT functions using the CORDIC approach, the proposed design requires about 60% less ROM than the conventional DA-based IDCT without using CORDIC. In our architecture the on-line algorithm is used to further reduce the area and to enhance the computation speed. The core operates on blocks of 8/spl times/8 pixels, with 12-bit and 8-bit precision for inputs and outputs, respectively. The proposed design has been synthesized by using 0.35-/spl mu/m CMOS technology. The simulation results show that the core for IDCT can run at 150 MHz with 60 Mpixel/s throughput, while meeting the requirement of the H.26x standard.