Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices

Christoph Gerum, Adrian Frischknecht, T. Hald, Paul Palomero Bernardo, Konstantin Lübeck, O. Bringmann
{"title":"Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices","authors":"Christoph Gerum, Adrian Frischknecht, T. Hald, Paul Palomero Bernardo, Konstantin Lübeck, O. Bringmann","doi":"10.1109/DSD57027.2022.00056","DOIUrl":null,"url":null,"abstract":"The increasing spread of artificial neural networks does not stop at ultralow-power edge devices. However, these very often have high computational demand and require specialized hardware accelerators to ensure the design meets power and performance constraints. The manual optimization of neural networks along with the corresponding hardware accelerators can be very challenging. This paper presents HANNAH (Hardware Accelerator and Neural Network seArcH), a framework for automated and combined hardware/software co-design of deep neural networks and hardware accelerators for resource and power-constrained edge devices. The optimization approach uses an evolution-based search algorithm, a neural network template technique and analytical KPI models for the configurable UltraTrail hardware accelerator template in order to find an optimized neural network and accelerator configuration. We demonstrate that HANNAH can find suitable neural networks with minimized power consumption and high accuracy for different audio classification tasks such as single-class wake word detection, multi-class keyword detection and voice activity detection, which are superior to the related work.","PeriodicalId":211723,"journal":{"name":"2022 25th Euromicro Conference on Digital System Design (DSD)","volume":"368 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 25th Euromicro Conference on Digital System Design (DSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD57027.2022.00056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

The increasing spread of artificial neural networks does not stop at ultralow-power edge devices. However, these very often have high computational demand and require specialized hardware accelerators to ensure the design meets power and performance constraints. The manual optimization of neural networks along with the corresponding hardware accelerators can be very challenging. This paper presents HANNAH (Hardware Accelerator and Neural Network seArcH), a framework for automated and combined hardware/software co-design of deep neural networks and hardware accelerators for resource and power-constrained edge devices. The optimization approach uses an evolution-based search algorithm, a neural network template technique and analytical KPI models for the configurable UltraTrail hardware accelerator template in order to find an optimized neural network and accelerator configuration. We demonstrate that HANNAH can find suitable neural networks with minimized power consumption and high accuracy for different audio classification tasks such as single-class wake word detection, multi-class keyword detection and voice activity detection, which are superior to the related work.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
超低功耗音频处理器件的硬件加速器与神经网络协同优化
人工神经网络的日益普及并不局限于超低功耗的边缘设备。然而,这些通常具有很高的计算需求,并且需要专门的硬件加速器来确保设计满足功率和性能限制。人工优化神经网络以及相应的硬件加速器是非常具有挑战性的。本文介绍了HANNAH(硬件加速器和神经网络搜索),这是一个用于资源和功率受限边缘设备的深度神经网络和硬件加速器的自动化和组合硬件/软件协同设计的框架。优化方法采用基于进化的搜索算法、神经网络模板技术和分析KPI模型,对可配置的UltraTrail硬件加速器模板进行优化,以找到优化的神经网络和加速器配置。我们证明了HANNAH可以在单类唤醒词检测、多类关键字检测和语音活动检测等不同的音频分类任务中找到功耗最小、准确率高的合适神经网络,优于相关工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1