Building n-bit ADC using n 1-bit new general ADC cell architecture

Abstract

This work introduces a new general architecture for an analog to digital converter (ADC) cell. Each ADC cell generates one digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage is suitable to be used as an input for another ADC cell in order to produce another digital output bit. This new ADC cell architecture is used as a building block to construct n-bit ADC. This n-bit ADC architecture is realized using cascaded n ADC cells and generates parallel digital output. A sample circuit realization is presented for the n-bit ADC and supported by simulation results. The ADC produces clean digital output when simulated at 50 Msample/sec.