An 8-bit 3.5 GS/s Current Steering DAC for Wireless Applications

Mohamed Taha, Khaled M. Morsi, Ahmed A. Naguib
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Abstract

A segmented 8-bit 3.54 GS/s current-steering digital-to-analog converter (CSDAC) designed and simulated in 130 nm CMOS technology. The spurious-free dynamic range (SFDR) that represents the CSDAC linearity is ranged from 65.7 dB at 11 MHz signal frequency to 54 dB at 1.770 GHz with an effective number of bits (ENOB) equals to 7.97 bits at a low frequency while degraded across the input frequency to reach 7.67 bit at 1.77 GHz.
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用于无线应用的8位3.5 GS/s电流转向DAC
采用130 nm CMOS技术设计并仿真了一种分段式8位3.54 GS/s电流转向数模转换器(CSDAC)。代表CSDAC线性度的无杂散动态范围(SFDR)范围从11 MHz信号频率下的65.7 dB到1.770 GHz信号频率下的54 dB,有效比特数(ENOB)在低频时等于7.97比特,而在1.77 GHz输入频率下降低到7.67比特。
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