Equalization tuning and system validation on cascaded re-drivers for 6Gbps storage applications

Abstract

Equalization (EQ) tuning methodology and system validation strategy on cascaded re-drivers for 6Gbps SAS and SATA application are discussed in this paper. DOE (Design of Experiment) is applied in the EQ tuning process on the TX link for SATA Gen3 applications and on the RX link for these applications that the eye diagram inside the host silicon can be accessed. Eye diagram measurements are the primary choice of designers to know the design margin. For these designs whose eye diagram are not available, BER (Bit Error Rate) test has to be applied although it can't tell any design margin information with a positive BER report. It is a good practice to do BER test under four corners (high, low voltage and high, low temperature) and skew'ed silicon, a pass BER report in these corner cases can provide additional confidence on the system.