Performance modeling of the modified mesh-connected parallel computer

Abstract

A message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is designed to be general-purpose parallel architecture suitable for wafer-scale integration. Generalized stochastic Petri nets (GSPNs) are used to model the behavior of the MMCPC. The GSPN performance modeling results show a need for a new processing element (PE). A PE architecture, able to handle data processing and message passing concurrently, is proposed, and the silicon overhead is estimated in comparison with transputerlike PEs. Based on the proposed PE, optimum sizes of the MMCPC for different program structures are derived. A two-dimensional fast Fourier transform problem is used as an example to demonstrate that the MMCPC is a cost-effective performance-enhancement architecture to a real problem.<>