Mapping Precedence-Constrained Simulation Tasks for a Parallel Environment

Abstract

The Mapping Problem Classical results on the deterministic precedence- constrained scheduling problem are almost exclusively concerned with a single iteration of the task system. This paper explores the problem of mapping deter- ministic tasks to processors in a parallel simulation environment, with each task iterating multiple times. Counterexamples are shown to demonstrate that mul- tiple passes through an optimal mapping for one iter- ation of a task system may produce less-than-optimal results when compared to mappings based on the it- erative nature of the simulation. A level strategy for assigning iterative tasks to processors is developed, and theoretical and experimental results are discussed for different mapping strategies in a VHDL simulation. This paper examines the classical multiprocessor scheduling problem for application to deterministic simulation systems. The tasks in these systems are characterized by iterative executions: each task exe- cutes more than once in the course of a simulation run. The general task scheduling problem and its relation- ship to the mapping problem for simulation tasks are introduced. The problem space is constrained, lim- iting the scope of the study to systems which map equal-execution time tasks into identical processors. A theoretical basis for the level strategy of iterative task assignment is summarized, and a polynomial- time algorithm based on this strategy is given. The results of hypercube experiments based on different mapping strategies are discussed with application to VHDL logic simulation.