Scalable temporally predictable memory structures

Abstract

Faster processors are used to tackle larger problems which typically require a larger memory. Unfortunately this prohibits memory access latency from scaling with processor speed, Consequently, multiple levels of caching are employed which utilise temporal and spatial locality of reference to bridge the performance gap. However, cache performance is difficult to predict which is problematic for hard real-time systems. A tree memory structure, whose access frequency, rather than latency, can scale with processor speed, is proposed, together with a scalable memory module base virtual addressing mechanism and page based memory protection using capabilities. It is concluded that a multi-threaded processor would be desirable to utilise the concurrency of hard real-time applications to tolerate the latency of the memory tree.<>