Optimizing method of C compiler for TRON architecture

Abstract

A description is given of the optimizing methods used in the ANSI-C compiler for the chip based on the TRON architecture. This C compiler is designed for the TLCS-90000/TX series microprocessors. For the C compiler, unique optimizing methods for the TRON architecture are used in the routines for optimization of intermediate language and code generation, in addition to the traditional global optimizing methods, such as copy propagation, loop optimization and register calling convention. Thus the compiling performance was improved. The unique features of the TRON architecture are: chained addressing mode, and the ACB and SSTR instructions. Finally, the performance of the optimizing compiler is evaluated in the terms of the execution time and object code size.<>