Internal matching circuit design of RF LDMOS power transistor

Abstract

This paper reports an optimized design of internal matching circuit for RF LDMOS power transistors. Efforts are mainly focused on the implementation of output internal matching circuit design, where a Shunt-L network structure is adopted. Computer-aided design (CAD) tools are employed to help rearrange the layout of bonding wire arrays to achieve a more uniform current distribution. Consequently, better robustness and RF performance can be obtained at the same time. With this technique, a RF LDMOS power transistor used at 2.14GHz is realized with saturation power of 51.3dBm and maximum efficiency of 63.8%.