{"title":"A proposal for a fault-tolerant binary hypercube architecture","authors":"Siu-Cheung Chau, A. L. Liestman","doi":"10.1109/FTCS.1989.105587","DOIUrl":null,"url":null,"abstract":"A modular fault-tolerant binary hypercube architecture is proposed that uses redundant processors and is suitable for use in long-life unmaintained applications. Each module initially contains 2/sup i/ (for any >or=0) active processors and k spare processors and is constructed so that each of the spare processors can replace any of the active processors (or any of the other spares) within the module. Thus, the module can tolerate up to k processor faults. This scheme is compared to previously proposed fault-tolerant binary hypercube architectures. It is shown that the scheme can achieve the same level of reliability as other proposed schemes while using significantly fewer spares.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"50","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTCS.1989.105587","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 50
Abstract
A modular fault-tolerant binary hypercube architecture is proposed that uses redundant processors and is suitable for use in long-life unmaintained applications. Each module initially contains 2/sup i/ (for any >or=0) active processors and k spare processors and is constructed so that each of the spare processors can replace any of the active processors (or any of the other spares) within the module. Thus, the module can tolerate up to k processor faults. This scheme is compared to previously proposed fault-tolerant binary hypercube architectures. It is shown that the scheme can achieve the same level of reliability as other proposed schemes while using significantly fewer spares.<>
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