A new table based modelling of 28nm fully depleted silicon-on insulator (FDSOI)

2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2016-06-27 DOI:10.1109/SMACD.2016.7520746

Abdelgader M. Abdalla, Jonathan Rodriguez

引用次数: 4

Abstract

In this work, a multivariate interpolation lookup tables (LUTs) model for nanometer CMOS transistors is presented. A novel lookup-table (LUT) method, which is based on a multivariate Neville's algorithm for the current-voltage (I-V) and Capacitance-voltage (C-V) characteristics of a transistor, is proposed for the simulation of MOS transistor circuits. The simulation speed is noted to be significantly enhanced with sufficient accuracy via a dynamic programming procedure with the implementation of the proposed approach compared to the current state of the art models. Simulation results are implemented in a 28-nm fully depleted SOI technology (FDSOI). Compared to simulations with both the BSIMSOI model and the Lagrange interpolation lookup table, the computation time of the proposed approach can be reduced by 8.X and beyond in transient analysis.

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基于表格的28nm全贫硅绝缘体(FDSOI)模型

在这项工作中，提出了一个纳米CMOS晶体管的多元插值查找表模型。提出了一种基于多元奈维尔算法的查找表法(LUT)，用于MOS晶体管电路的仿真。与目前的先进模型相比，通过动态规划程序实施所提出的方法，可以显着提高仿真速度，并具有足够的精度。仿真结果在28纳米全耗尽SOI技术(FDSOI)中实现。与BSIMSOI模型和拉格朗日插值查找表的模拟结果相比，该方法的计算时间缩短了8倍。在瞬态分析中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

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