Random and Triple burst error correction code with low redundancy for Network-on-Chip link

Abstract

Error correction code with higher error correction capability with minimum redundant bit is the need of the day for on-chip interconnect link. Hence, in this paper an energy competent low redundancy error correction code with more error correction is proposed. The proposed error correction code is capable of correcting single random error as well as burst errors of up to triple bits. The proposed code has redundancy bits same as that of the single error correction- double error detection (SEC-DED) Hamming code and has small increase in the decoder complexity to make it to correct up to triple burst errors. The proposed code has been implemented using 180 nm technology using verilog coding. The performance of the code has been assessed based on area and power consumption of codec as well as router placed with codec and without codec. The proposed code occupies up to 29 % less area compared to 25% less power compared to the existing codes. Also the performance of the code for residual error rate, link swing voltage and link power consumption have been analyzed and is found to be minimum compared to other codes.