Low power conditional sum adder using pass logic topology

Abstract

The Low Power Conditional Sum Adder (CSA) has been analyzed using various logic styles. Pass logic topology implementation offered low power delay product and occupied less silicon area compared to other topologies. A test chip for two versions of the CSA using pass logic and standard CMOS has been designed and fabricated using 0.5 /spl mu/ CMOS technology. Test results indicate that 50% power saving has been achieved in Pass Logic CSA.