A reconfigurable VLSI array for reliability and yield enhancement

Abstract

The fault-tolerance scheme consists of two phases: testing and locating faults (fault diagnosis), and reconfiguration. The first phase uses an online error-detection technique that achieves a compromise between the space and time redundancy approaches. This technique reduces the rollback time considerably and is capable of detecting permanent as well as transient faults. Reconfiguration consists of mapping the function of the faulty processor element onto an adjacent nonfaulty neighbor, which is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. A reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.<>