A novel fault tolerant approach for SRAM-based FPGAs

Jian Xu, P. Si, Wei-Kang Huang, F. Lombardi
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引用次数: 6

Abstract

This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature.
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一种基于sram的fpga容错方法
提出了一种新的基于sram的fpga容错方法。该方法包括容错体系结构及其相关的路由过程。在该方法中,clb和互连的开销都被考虑在内。该方法具有容错路由过程简单、耗时短等优点。仿真结果表明,该方法的开销比以往技术文献中发现的方法要低。
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