Evaluating the scalability of test buses

Abstract

Intra-chip communication architectures evolved from buses to networks-on-chip, in order to provide design scalability and increased bandwidth. However, the predominant test architecture for SoCs is still based on buses. While this approach presents advantages, such as simple design and a mature set of automation tools, its scalability is questionable. This paper evaluates such aspect by synthesizing SoCs of different sizes (with more than 100 cores) to layout level and extracting accurate results in terms of wire length, capacitance, and delay. The results compare the wiring for test buses and for NoC links, indicating that these test buses have limited scalability (highly irregular wire lengths and long wires) and may not be suitable for testing future SoCs with hundreds of cores. Finally, we discuss advantages and drawbacks of some approaches proposed in the literature. This discussion might give directions towards new scalable SoC test architectural models.