Application Specific VLIW Processors with Power-Saving Mode Via Variable Arithmetic Accuracy

Abstract

This paper discusses an idea for power-saving mode in application specific processors in the domain of digital signal processing. This idea is based on a multiple (in practice double) accumulator model, which is used in order to obtain high accuracy in a series of floating-point additions. The goal is to introduce a possibility of reducing the power consumption without reducing the functionality. In the case of low power, instead of decreasing the performance of the system or shutting down the system, as it is done in other approaches, in our concept merely the accuracy of the floating point accumulation is reduced. Therefore although the quality of service is reduced, the performance is not.