Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

Abstract

The ASIC designs are growing larger everyday. It is very hard to simulate these designs because the simulation time has risen tremendously. An alternate solution is to partition the large design into modules and perform incremental simulation. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of large ASICs. On the other hand, since the introduction of FPGAs, they have been playing an important role in ASIC design cycle. But due to very large size of today's ASIC designs (millions of gates) compared to FPGAs, it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. This paper takes a large RTL design of an ASIC into consideration, analyzes the size of each module in terms of number of CLBs, I/Os, flip-flops, latches and applies the algorithm to partition it automatically into minimum number of FPGAs.