Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit

Zafar Takhirov, B. Nazer, A. Joshi
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引用次数: 17

Abstract

Voltage scaling is commonly used to reduce the energy consumption of digital CMOS logic. However, as the supply voltage decreases, transistor switching times increase, leading to intersymbol interference (ISI) between successive outputs of the digital logic. This limits the amount of voltage scaling that can be applied for a target performance. We describe a novel circuit-level technique that couples feedback equalization with a Schmitt trigger (FEST) to suppress this ISI, which in turn enables further voltage scaling while ensuring reliable operation at the desired target performance. For a 4-bit, 22 nm Kogge-Stone adder designed for 2 GHz operation, the proposed technique lowers the critical voltage (beyond which frequent timing errors occur) from 580 mV (nominal design) to 510 mV (design with FEST circuit), providing a 20% decrease in energy per operation. We also apply this technique to a 3-tap 4-bit finite impulse response (FIR) filter operating at 500 MHz, and observe that the critical voltage drops from 680 mV (nominal design) to 510 mV (design with FEST circuit) and the energy per operation can be decreased by up to 40%.
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利用施密特触发器(FEST)电路的反馈均衡降低数字逻辑中的误差
电压缩放通常用于降低数字CMOS逻辑的能耗。然而,随着电源电压的降低,晶体管开关次数增加,导致数字逻辑连续输出之间的符号间干扰(ISI)。这限制了可以应用于目标性能的电压缩放量。我们描述了一种新的电路级技术,该技术将反馈均衡与施密特触发器(FEST)耦合以抑制这种ISI,从而实现进一步的电压缩放,同时确保在期望的目标性能下可靠地运行。对于设计用于2 GHz工作的4位,22 nm Kogge-Stone加法器,所提出的技术将临界电压(超过该电压会发生频繁的时序错误)从580 mV(标称设计)降低到510 mV(采用FEST电路的设计),每次操作可减少20%的能量。我们还将该技术应用于工作在500 MHz的3抽头4位有限脉冲响应(FIR)滤波器,并观察到临界电压从680 mV(标称设计)降至510 mV(使用FEST电路设计),每次操作的能量可降低高达40%。
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