A Precise Interrupts Mechanism Based on Micro-Operation Tracing of Instruction Boundary for Embedded Processor

Abstract

Precise interrupts is a key technique of embedded processor, for assurance of properly executing and state resuming of the whole system. As interrupt occurs on the instruction boundary, pipeline flushing, interrupt transfer micro-program and interrupt handling routine are executed after the committing soon instruction finishes. This process spends lots of cycles to pre-fetch and decode instructions that will never be executed, and reduces the real time performance. Combined with the CISC processor execution characteristic of micro-operation, this paper proposes a precise interrupts mechanism based on Instruction Boundary Micro-operation Tracing, called IBMT. This technique inspects instruction boundary and interrupt window every clock cycle, and starts up the pipeline flushing, pre-fetch, interrupt transfer micro-program and interrupt handling routine in advance. As a result, 39.34% of the clock cycles can be saved at every interrupt acknowledgement.