Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Abstract

We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal segment growing. We analyze and optimize the size and shape trade-offs for the pixel block, and evaluate the proposed architecture by an FPGA. Altogether, the investigated architecture concepts reduce the area-time product by 52.3 % in comparison to a previously reported one-dimensional (1D) scanning architecture.