Jian Liu, Lin Lin, Xin Wang, H Zhao, He Tang, Q. Fang, Albert Z. H. Wang, Liwu Yang, Haolu Xie, S. Fan, B. Zhao, Gary Zhang, Xingang Wang
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引用次数: 3
Abstract
This paper reports a tunable low triggering voltage, dual-directional SCR ESD protection structure in CMOS for RF ICs. A new embedded gate-coupling technique is used to reduce and adjust its triggering voltage. Experiment shows a low discharging resistance of ∼0.26Ω, low leakage current of ∼0.19nA, low parasitic capacitance of ∼150fF and ultra fast response time of ∼100pS. This structure achieves ESD protection of >9.20kV HBM and >500V CDM for a 90µm device. A high ESD protection to Si ratio of ESDV∼8.17V/µm2 is obtained for RF IC applications.
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