A Novel Architecture for Implementation of Quasi Delay Insensitive Finite State Machines

Abstract

Due to the increasing demand for mobile devices, the search for ultra-low-power projects is becoming a priority. One technique that allows a strong reduction of circuits dissipated power is the sub-threshold voltage operation, but it leads to some drawbacks. The QDI (Quasi Delay Insensitive) asynchronous circuits class shows to be an interesting solution to these problems, when compared to synchronous circuits and in CMOS-UDSM (Ultra Deep Sub-Micron) technology. Asynchronous finite state machines (AFSMs) are important components in an asynchronous system. This paper proposes a new architecture for QDI AFSMs described in Extended Burst-Mode specification, implemented in the dual-rail style using basic gates and memory based on RS latches. The resulting XBM_AFSMs are QDI, so they can operate in sub-threshold voltage. The architecture is presented through the case study and the obtained QDI_XBM_AFSM presents for three benchmarks an average reduction of 24.4%, and 48.3%, 49.6% and 49.2% respectively, latency time, number of LUTs, dynamic power and static power, when compared with four QDI controllers of the literature.