{"title":"Deconstructing commit","authors":"Gordon B. Bell, Mikko H. Lipasti","doi":"10.1109/ISPASS.2004.1291357","DOIUrl":null,"url":null,"abstract":"Many modern processors execute instructions out of their original program order to exploit instruction-level parallelism and achieve higher performance. However even though instructions can execute in an arbitrary order, they must eventually commit, or retire from execution, in program order. This constraint provides a safety mechanism to ensure that mis-speculated instructions are not inadvertently committed, but can consume valuable processor resources and severely limit the degree of parallelism exposed in a program. We assert that such a constraint is overly conservative, and propose conditions under which it can be relaxed. This paper deconstructs the notion of commit in an out-of-order processor, and examines the set of necessary conditions under which instructions can be permitted to retire out of program order. It provides a detailed analysis of the frequency and relative importance of these conditions, and discusses microarchitectural modifications that relax the in-order commit requirement. Overall, we found that for a given set of processor resources our technique achieves speedups of up to 68% and 8% for floating point and integer benchmarks, respectively. Conversely, because out-of-order commit allows more efficient utilization of cycle-time limiting resources, it can alternatively enable simpler designs with potentially higher clock frequencies.","PeriodicalId":188291,"journal":{"name":"IEEE International Symposium on - ISPASS Performance Analysis of Systems and Software, 2004","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"46","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on - ISPASS Performance Analysis of Systems and Software, 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPASS.2004.1291357","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 46

Abstract

Many modern processors execute instructions out of their original program order to exploit instruction-level parallelism and achieve higher performance. However even though instructions can execute in an arbitrary order, they must eventually commit, or retire from execution, in program order. This constraint provides a safety mechanism to ensure that mis-speculated instructions are not inadvertently committed, but can consume valuable processor resources and severely limit the degree of parallelism exposed in a program. We assert that such a constraint is overly conservative, and propose conditions under which it can be relaxed. This paper deconstructs the notion of commit in an out-of-order processor, and examines the set of necessary conditions under which instructions can be permitted to retire out of program order. It provides a detailed analysis of the frequency and relative importance of these conditions, and discusses microarchitectural modifications that relax the in-order commit requirement. Overall, we found that for a given set of processor resources our technique achieves speedups of up to 68% and 8% for floating point and integer benchmarks, respectively. Conversely, because out-of-order commit allows more efficient utilization of cycle-time limiting resources, it can alternatively enable simpler designs with potentially higher clock frequencies.
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解构提交
许多现代处理器在其原始程序顺序之外执行指令,以利用指令级并行性并获得更高的性能。然而,即使指令可以按任意顺序执行,它们最终也必须按程序顺序提交或退出执行。此约束提供了一种安全机制,以确保不会无意中提交错误推测的指令,但会消耗宝贵的处理器资源,并严重限制程序中暴露的并行度。我们认为这种限制过于保守,并提出可以放宽的条件。本文解构了乱序处理器中提交的概念,并研究了允许指令按程序顺序退出的必要条件集。本文详细分析了这些条件的频率和相对重要性,并讨论了放松按顺序提交要求的微架构修改。总的来说,我们发现对于给定的一组处理器资源,我们的技术在浮点和整数基准测试中分别实现了高达68%和8%的加速。相反,由于乱序提交允许更有效地利用周期时间限制资源,因此它可以使用可能更高的时钟频率实现更简单的设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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