{"title":"Verilog-model ALU microprocessor 6502 at the base MPGA 5503HM5 (CAD VLSI Kovcheg 3.02)","authors":"B. Bogomolov","doi":"10.1109/APEIE.2016.7802253","DOIUrl":null,"url":null,"abstract":"For the first time created a Verilog-model ALU microprocessor 6502 company MOS Technology (USA) based MPGA 5503HM5 using CAD VLSI Kovcheg 3.02. It carried out a complete ALU design cycle, including the simulation of the formation of a truth table and topology. It is shown that the library 5503 is functionally complete and supports the effective development of all the constituent elements of the ALU microprocessor 6502 based Verilog Netlist.","PeriodicalId":363890,"journal":{"name":"2016 13th International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 13th International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEIE.2016.7802253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
For the first time created a Verilog-model ALU microprocessor 6502 company MOS Technology (USA) based MPGA 5503HM5 using CAD VLSI Kovcheg 3.02. It carried out a complete ALU design cycle, including the simulation of the formation of a truth table and topology. It is shown that the library 5503 is functionally complete and supports the effective development of all the constituent elements of the ALU microprocessor 6502 based Verilog Netlist.