A High-Performance Parallel Hardware Architecture of SHA-256 Hash in ASIC

Abstract

The SHA-256 algorithm is used to ensure the integrity and authenticity of data in order to achieve a good security thus is playing an important role in various applications, such as e-transactions and bitcoins. The SHA-256 computation capacity is a main research direction of Hashing Algorithm. In order to improve the computation capacity of hardware, the proposed design first uses pipeline principle and circuitry of timing prediction to find a most efficient architecture for implementation. Then it is optimized with hash function and hardware characteristics to give a high-performance hardware architecture of SHA-256 hash. Three pipelines are used to replace the critical path in the round functions which can shorten the timing path, and divide the computation chain into independent steps. Multi-computation of SHA-256 is working in parallel pipelines, indicating that the computation capacity can be 3 times of that with standard SHA-256 implementation. The proposed SHA-256 hardware architecture has been implemented and synthesized with Intel 14nm technology. Simulation and synthesis results show the proposed SHA-256 hashing throughput can be improved by 3 times with 50.7% power reduction, at an area cost of 2.9 times compared to that of the standard implementation.