{"title":"Design of an active-inductor dual-loop frequency synthesizer","authors":"S. Sinha, M. du Plessis","doi":"10.1109/EDMO.2004.1412399","DOIUrl":null,"url":null,"abstract":"High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 /spl mu/m BiCMOS process, simulations showed a phase noise of -117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.","PeriodicalId":424447,"journal":{"name":"12th International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2004. EDMO 2004.","volume":"330 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2004. EDMO 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDMO.2004.1412399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 /spl mu/m BiCMOS process, simulations showed a phase noise of -117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.