HEVC in-loop filters GPU parallelization in embedded systems

D. Souza, A. Ilic, N. Roma, L. Sousa
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引用次数: 17

Abstract

The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embedded systems, mobile and battery supplied devices. To circumvent this limitation, this paper proposes the exploitation of embedded GPU devices already equipping many state of the art SoCs to accelerate the HEVC in-loop filters (i.e. deblocking filter and sample adaptive offset). The presented approaches comprehensively exploit both fine and coarse-grained parallelization opportunities of these filters in an NVIDIA Tegra GPU.According to the conducted experimental evaluation, the proposed approach showed to be a remarkable strategy to satisfy the real-time requirements of the HEVC decoder, being able to filter each Ultra HD 4K intra frame in less than 20 ms (about 50 fps).
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嵌入式系统中HEVC环内滤波GPU并行化
最新的HEVC标准所提供的编码效率和视觉质量的提高,主要是以编码器和解码器的计算复杂度显著增加为代价的。然而,这种增加的复杂性极大地影响了该标准在计算和能量受限设备中的实现,包括嵌入式系统、移动设备和电池供电设备。为了规避这一限制,本文提出利用嵌入式GPU设备已经装备了许多最先进的soc来加速HEVC环内滤波器(即去块滤波器和样本自适应偏移)。提出的方法综合利用了NVIDIA Tegra GPU中这些滤波器的细粒度和粗粒度并行化机会。实验结果表明,该方法能够在不到20 ms(约50 fps)的时间内过滤出每个超高清4K帧内帧,能够满足HEVC解码器的实时性要求。
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