Xin Wang, S. Fan, B. Qin, Lin Lin, Q. Fang, H Zhao, He Tang, Jianlin Liu, Zitao Shi, Albert Wang, Liwu Yang, Yuhua Cheng
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引用次数: 2
Abstract
This paper presents design of an all-digital fully-integrated 5th-order Gaussian pulse generator (PG) for full band (3.1GHz–10.6GHz) impulse radio ultra wideband (IR-UWB) transceiver SoC. The design is implemented in a foundry 0.18µm CMOS process. New FCC effective isotropic radiated power (EIRP) aware design technique is used to optimize the PG. Measurement shows peak pulse amplitude of 533mV at 100MHz pulse repeating frequency (PRF) and pulse width of 418pS. 5kV ESD protection is integrated. This 5th Gaussian PG consumes the lowest reported power of 0.05pJ/p-mV and support data rate to 2.4Gbps.
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