Control unit synthesis targeting low-power processors

Abstract

With demands for reliability and further integration, reducing power consumption becomes a critical concern in today's processor design. Considering the different techniques to minimize power consumption and promote system's reliability, reducing switching activity of CMOS circuits is a promising area to be explored. Motivated by these, we propose two optimization schemes which can be incorporated into processor's control unit synthesis to lower power dissipation. The first one, a low-power decoding scheme, utilizes graph embedding and logic minimization techniques to refine the decoding structure in processor's control unit. To get further optimization for those control units in nanoprogrammed or microprogrammed architecture, the second scheme is proposed to optimally assign ZERO or ONE to the don't-care bits distributed in nanocontrol memory or control memory, to significantly reduce switching activity within the control unit and/or on the path from control unit to data processing unit. To achieve these two goals efficiently, we have used pseudo-Boolean programming to optimize the synthesis parameters. Based on a subset of 8086 instruction set, experimental results show that 15.8 percent improvement is obtained by properly encoding instruction opcodes, and 4.9 to 16.6 percent improvement can be obtained from a optimal don't-care bits assignment.