Hierarchical Cluster-Based Irregular Topology Customization for Networks-on-Chip

Abstract

In this paper, a hierarchical cluster-based irregular topology customization method is proposed for Networks-on-Chip (NoC). This method contains three steps: (1) partitioning IPs into many hierarchical clusters; (2) generating a core network; (3) deleting redundant edge routers. Results show that the irregular topologies generated by our hierarchical cluster-based method consume less power when satisfying the bandwidth and port number constraints. Compared with the previous method, our method can save about 15.41% of power averagely for all benchmark applications. Particularly, for MPEG 4 decoder, our method can save 31.62% of power.